1. Field of Invention
The present invention relates to a chip package and fabricating method thereof, and more particularly, to a chip package and fabricating method thereof with at least one elastic element.
2. Brief Discussion of the Related Art
Accompanying to the development of semiconductor device and process, the chips trends to high density and small wire width. More and more functionalities are integrated within the same scale size. That is, more signal terminals are needed for the chip to connect with outside and more heat dissipated from the same area. In order to satisfy these requirements, a chip package also trends to a flip-chip technology.
FIG. 1 shows a lateral view of a conventional flip-chip package. The package at least includes a chip 10 and a chip carrier 20. The chip 10 has a first surface 11 and a plurality of pads 13 disposed on the first surface 11. The first surface 11 is located at one side of the chip 10 and so-called an active surface. A bump 30 is disposed on each pad 13 of the chip 10, which is made of metal or alloy such as lead-tin alloy. The bumps 30 are then soldered with the chip carrier 20, the pads 13 are electrically connected with the chip carrier 20, and the signals from the chip 10 are transmitted to the chip carrier 20 through the bumps 30. Then the chip 10 is connected to a circuit board (not shown) by the internal circuit and a plurality of solder balls 21 of the chip carrier 20. The active surface 11 of the chip 10 faces to the chip carrier 20 and the bonding is so-called flip-chip package technology. In order to protect and enhance the connection between the chip 10, the bumps 30 and the chip carrier 20, the package further has an insulating material 40 disposed between the chip 10 and the chip carrier 20. The insulating material 40 surrounds the bumps 30 and covers a portion of the chip 10. The chip has a second surface 12, so-called a back surface, located at the other side of the chip 10. The second surface 12 is thus not covered by the insulating material 40.
Due to the substrate of the chip 10 is made of silicon and the material property is brittle and cannot sustain the collisions, the chip 10 is supported and protected by the chip carrier 20 and then to be packaged. However, the package by flip-chip bonding cannot protect the chip 10 well because the second surface 12 of the chip 10 is exposed outside. The chip 10 may be damaged in the following processes and operations especially the cracks in the edge of the second surface 12 caused by the collisions. The edge of the chip is possible to be cracked by the collisions during wafer cutting, testing, packaging, manufacture and shipment of end product. The cracks in the edge of the chip will degrade the reliability and induce the malfunction of the chip. Such an insufficient protection to the chip will raise the damage possibility and cause the return ratio and cost increasing.
FIG. 2 shows a prior art to avoid the edge of the second surface of the chip from damage. The package includes a chip 10, a chip carrier 20, a plurality of bumps 30 electrically connected with the chip 10 and the chip carrier 20, an insulating material 40 surrounded the bumps 30 and covered a portion of the chip 10, and a reinforced dam 50 surrounded the edge of the chip 10. The reinforced dam 50 is fixed on the chip carrier 20 and located at the same side with the chip 10. The edge of the chip 10 can avoid the lateral collisions to the chip 10 by the reinforced dam 50. However, the reinforced dam 50 disposed on the chip carrier 20 will occupy the space of the chip carrier 20 and the scale size of the chip carrier 20 is limited and cannot be shrunk down. In addition, if the height of the reinforced dam 50 is higher than that of the chip 10, the heat dissipated from the chip 10 will be blocked from dissipating to lateral direction and lower thermal dissipating efficiency caused by the heatsink (not shown) on the second surface 12 of the chip 10 is not effectively contacted with the chip 10. The whole thermal dissipating efficiency of the chip 10 is thus reduced. If the height of the reinforced dam 50 is lower than that of the chip 10, the edge of the chip 10 is not well-protected and the damage to the edge of the chip 10 cannot be effectively reduced.
It is therefore an important subject of the present invention to provide a chip package and fabricating method thereof to simultaneously achieve well protection and thermal dissipation to the chip.